////////////////////////////////////////////////
///file: clk_rst_gen.v
///Author: Qyw
////////////////////////////////////////////

module clk_rst_gen(//input
					clk_in,
					arst_n,
					//output
					sys_rst_n,
					clk_125k,
					clk_250k,
					clk_1m
					);

input		clk_in;
input		arst_n;
output		sys_rst_n;
output		clk_125k;
output      clk_250k;
output      clk_1m;

wire		pll_rst,
			sync_clk_in_rst_n,
			lock;
wire        clk_250k;
reg	[2:0]	div;
reg	[1:0]	rst_r_clk_1m,
			rst_r_clk_in;


assign pll_rst = ~rst_r_clk_in[1];
assign sync_clk_in_rst_n = rst_r_clk_in[1] & lock;
assign sys_rst_n = rst_r_clk_1m[1];
assign clk_125k = div > 3'd3;

pll pll_ins(//input
			.areset(pll_rst),
			.inclk0(clk_in),
			
			//output
			.c0(clk_1m),
			.c1(clk_250k),
			.locked(lock)
			);

always @(posedge clk_in or negedge arst_n)
	if(~arst_n)
		rst_r_clk_in <= 2'b00;
	else
		rst_r_clk_in <= {rst_r_clk_in[0], 1'b1};

always @(posedge clk_1m or negedge sync_clk_in_rst_n)
	if(~sync_clk_in_rst_n)
		rst_r_clk_1m <= 2'b00;
	else
		rst_r_clk_1m <= {rst_r_clk_1m[0], 1'b1};


always @(posedge clk_1m or negedge sys_rst_n)
	if(~sys_rst_n)
		div <= 3'b000;
	else
		div <= div + 1'b1;


endmodule
